Conventional electronic memories may be implemented by arrays of discrete memory cells. Many types of memory cells currently exist. Each type of memory cell may be associated with one or more methods for writing a value and reading a stored value.
FIG. 1 shows a cross-sectional view of floating-body dynamic random access memory (FBDRAM) memory cell 1. Cell 1 comprises a single transistor fabricated upon p-type substrate 2 and n-type well 3. The transistor includes n+-type source 4, p-type body 5 and n+-type drain 6. Oxide 7 is disposed over body 5 and gate 8 overlays oxide 7.
The value stored by cell 1 is determined by a concentration of charge carriers within body 5. Accordingly, it is important that body 5 retain charge carriers so as to preserve the stored value. To improve charge retention within body 5, body 5 is isolated from adjacent memory cells by oxides 9 and by other unshown oxides disposed in front of and behind the plane of FIG. 1. The isolating oxides may be fabricated using shallow trench isolation (STI) techniques.
FIG. 2 is a schematic diagram showing a 2×2 array of memory cells. It will be assumed that each of memory cells 10, 20, 30 and 40 is configured similarly to memory cell 1 of FIG. 1. The source of each memory cell is coupled to ground, the gate is coupled to a Word Line (WL), and the drain is coupled to a Bit Line (BL). According to conventional techniques, a “1” is written to a cell by applying a positive voltage to the gate via an appropriate Word Line, and by applying a positive voltage to the drain via an appropriate Bit Line. This biasing causes the cell to operate in saturation and thereby creates an impact ionization current that injects charge carriers into the body of the cell. The impact ionization current is depicted in FIG. 2 as a current source associated with each cell.
To write a “0”, a positive voltage is applied to the gate via an appropriate Word Line and a negative voltage is applied to the drain via an appropriate Bit Line. Charge carriers are thereby ejected from the body to the drain. Ejection of the charge carriers is depicted as a body-to-drain diode associated with each cell of FIG. 2.
Applying a negative voltage via a Bit Line may inadvertently discharge other memory cells that are coupled to the Bit Line. In a specific example, memory cell 20 is discharged by applying a positive voltage to Word Line WLB and by applying a negative voltage to Bit Line BLA. However, the negative voltage on Bit Line BLA may discharge the body of memory cell 10 even if Word Line WLA is “off”. These inadvertent effects may be reduced in some implementations by precisely controlling the gate and drain voltages during a discharge and by increasing the gate-to-body coupling of each memory cell (e.g., by fabricating each transistor using Silicon On Insulator (SOI) techniques). Such implementations may be inefficient in terms of one or more of fabrication cost, die footprint, operational tolerances, and other factors.